1. Field of the Invention
The present invention relates to a control driver and a display apparatus using the same.
2. Description of the Related Art
In recent years, mobile terminals such as a portable phone and a PDA (Personal Digital Assistant) are developed to have various useful functions, and various data can be displayed on a display screen of the mobile terminal. For example, the portable phone is provided with an E-mail function, a web viewing function, a photography function, an animation display function and so on, in addition to the telephone communication function. Image data of a large size can be displayed on the display screen of the portable phone in addition to text data.
FIG. 1 is a block diagram showing the mobile terminal to which a conventional control driver is applied. Referring to FIG. 1, the mobile terminal is composed of a display unit and an input unit (not shown). The input unit is operated by a user. The display unit is composed of an image drawing unit 101, a control driver 102, a display section 103, a gradation voltage generating circuit 104 and a gate line drive circuit 105. A CPU is exemplified as the image drawing unit 101. The control driver 102 is composed of a latch section (not shown), a memory control circuit 106, a display memory section 107, a latch section 108, a data line drive circuit 109 and a timing control circuit 110.
The image drawing unit 101 transfers the image data to the control driver 102, and the display memory section 107 stores the image data. The number of bits of each of pixels of the image data is 2 or more, and it is supposed that the number of bits of each pixel is 8 in this example. The display section 103 has the pixels which are defined by data lines and gate lines and arranged in a matrix. The display section 103 displays the image data for one screen.
The image drawing unit 101 outputs a timing control signal as a clock signal to the timing control circuit 110. The timing control circuit 110 generates and outputs timing signals to the memory control circuit 106, the latch section 108 and the gate line drive circuit 105 in response to the timing control signal from the image drawing unit 101. The memory control circuit 106, the latch section 108 and the gate line drive circuit 105 operate in synchronism with the timing signal.
The image drawing unit 101 outputs a memory control signal to the memory control circuit 106, when the image drawing unit 101 transfers the image data to the control driver 102. The memory control signal contains an image data size signal, and signals to control write and read operations of the image data into and from the display memory section 107. The memory control circuit 106 outputs a write control signal containing a write signal and an address to the display memory section 107 in response to the timing signal and the memory control signal. Thus, the image data from the image drawing unit 101 is stored in the display memory section 107. Also, when the image data is to be displayed on the display section 103, the image drawing unit 101 generates and output the memory control signal to the memory control circuit 106. The memory control circuit 106 generates and outputs a read control signal containing a read signal and an address to the display memory section 107 in response to the timing signal and the memory control signal. Thus, the image data is read out from the display memory section 107 for one display line, and the latch section 108 latches the image data for the one display line. The latch section 108 outputs the display data to the data line drive circuit 109 in response to the timing signal. The gradation voltage generating circuit 104 generates and outputs the gradation voltages for gradation-display of the display data to the data line drive circuit 109. The data line drive circuit 109 inputs the display data from the latch section 108, and drives the data lines of the display section 103 based on the display data and the gradation voltages from the gradation voltage generating circuit 104.
Now, it is supposed that the size of the image data is not larger than a size of the screen of the display section 103. In this case, in a write operation, the image drawing unit 101 transfers the image data to the control driver 102 in synchronism with the timing signal. The image data supplied from the image drawing unit 101 is stored in the display memory section 107 in response to the write control signal from the memory control circuit 106. In a read operation, when the image data is to be displayed to the display section 103, image data for one gate line is read out from the display memory section 107 in response to the read control signal supplied from the memory control circuit 106. The image data for the one gate line is latched by the latch section 108, and then displayed on the display section 103.
From a demand of miniaturization of the mobile terminal, the pixel size of the screen of the display section 103 is limited. When the mobile terminal receives the image data (containing an E-mail) having a size larger than the pixel size of the screen of the display section 103, the mobile terminal can not display the whole of image data on the display section 103. Therefore, the mobile terminal displays the image data while switching the display in response to a scroll instruction from the user. Now, it is supposed that the size of the image data is larger than that of the screen of the display section 103, and is composed of first image data and second image data.
In a first process when the size of the image data is larger than that of the screen of the display section 103, the image drawing unit 101 transfers the first image data to the control driver 102 in synchronism with the timing signal. The first image data is stored in the display memory section 107 in response to the display memory control signal from the memory control circuit 106.
In the first process, when the first image data is displayed on the display section 103, the image data for a gate line is read out from the display memory section 107 in response to the read memory control signal from the memory control circuit 106. The image data for the gate line read out from the display memory section 107 is outputted to the latch section 108 as display line data. The latch section 108 latches the display line data.
When the user to operates the input unit such that the second image data is to be displayed on the display section 103, a scroll instruction is issued and a second process is carried out. In the second process, the image drawing unit 101 transfers the second image data to the control driver 102 in synchronism with the timing signal. The second image data is stored in the display memory section 107 based on the write control signal from the memory control circuit 106.
In the second process, when the second image data is displayed on the display section 103, the image data for a gate line is read out from the display memory section 107 in response to the read control signal from the memory control circuit 106. The image data for the gate line read out from the display memory section 107 is outputted to the latch section 108 as the display line data. The latch section 108 latches the display line data.
FIG. 2 is a block diagram showing the structure of the display memory section 107 and the latch section 108 in the conventional control driver. The display memory section 107 contains a word line decoder 121 as a row decoder, a bit line decoder 122 as a column decoder, and memory cells 26. Word lines WLi 123 (1≦i≦m, m is the number of gate lines of the display section 103) are connected with the word line decoder 121. Pairs of bit lines Bj(k) 125 and Bj′(k) 125′ (1≦j≦n, n is the number of data lines of the display section 103, 0≦k≦p, p is the number of bits of the image data) are connected with the bit line decoder 122. Each memory cell 26 is defined by the word line and the pair of bit lines. The memory cells 26 are arranged in a matrix in a row direction and a column direction. The memory cells 26 are allocated in order from the most significant bit (bit 7) to the least significant bit (bit 0) for each pixel in a row direction. A sense amplifier 128(k) is provided for each of columns of the memory cells 26.
The latch section 108 contains a plurality of latch circuits. The latch circuits of the latch section 108 are provided for the columns of the memory cells 26 in order from the most significant bit to the least significant bit.
FIG. 3 is a circuit diagram showing the structure of a part of the display memory section 107 in the conventional control driver. FIG. 3 shows the columns for the bit 7 and bit 6, and the structures of the columns for the bit 7 to bit 0 in the display memory section 107 are the same. The columns contain a column selection section, a memory cell section, a precharge circuit section and a sense amplifier section. The structure of the column of the bit 7 will be described.
Referring to FIG. 3, in the column selection section, the bit 7 of a pixel of the image data latched by the latch section (not shown) is connected with bit lines Bj(7) of a pair via a switch SW111 and with the bit line Bj′(7) of the pair via an inverter I111 and a switch SW112. The switches SW111 and SW112 are turned on in response to the write signal WT supplied to the memory control circuit 106.
In the memory cell section, each of the memory cells 26 in the column of the memory cells for the bit 7 is connected with a corresponding word line WLi. Each memory cell 26 contains an N-channel MOS transistor T111, a latch element and an N-channel MOS transistor T112, which are connected in series between the bit lines Bj(7) and Bj′(7) of the pair. The latch element contains two inverters I112 and I113, which are connected in parallel in opposite directions. The gates of the N-channel MOS transistors T111 and T112 are connected with the corresponding word line WLi. The word line decoder 121 decodes a Y address of the write or read control signal to select one of the word lines WLi. also, the memory cell section is connected with the precharge circuit section via switches SW121 and SW122. The switches SW121 and SW122 are turned on a sense precharge control signal SPC supplied from the memory control circuit 106.
In the precharge circuit section, two P-channel MOS transistors T121 and T122 are connected between the bit lines Bj(7) and Bj′(7) of the pair, and a node between the two P-channel MOS transistors T121 and T122 is connected with the power supply voltage VDD. The gates of the two P-channel MOS transistor T121 and T122 are connected with a precharge signal PCB supplied from the memory control circuit 106. Thus, when the two P-channel MOS transistors T121 and T122 are turned on in response to the precharge signal PCB, the bit lines are precharged. Also, a P-channel MOS transistor T123 is connected between the bit lines Bj(7) and Bj′(7) of the pair. The gate of the P-channel MOS transistor T123 is connected with the precharge signal PCB. Thus, the potentials of the bit lines are equalized in response to the precharge signal PCB.
In the sense amplifier section, two P-channel MOS transistors T124 and T125 are connected between the bit lines Bj(7) and Bj′(7) of the pair, and a node between the two P-channel MOS transistors T124 and T125 is connected with the power supply voltage VDD via a switch SW131. Also, two N-channel MOS transistors T113 and T114 are connected between the bit lines Bj(7) and Bj′(7) of the pair, and a node between the two N-channel MOS transistors T113 and T114 is connected with the ground GND via a switch SW132. The gates of the P-channel MOS transistor T125 and N-channel MOS transistor T114 are connected with the bit line Bj(7) of the pair, and the gates of the P-channel MOS transistor T124 and N-channel MOS transistor T113 are connected with the bit line Bj′(7) of the pair. The switches SW131 and SW132 are turned on in response to a sense amplifier enable signal SE supplied from the memory control circuit 106. Thus, when the potential of the bit line Bj(7) is higher than that of the bit line Bj′(7), the P-channel MOS transistor T124 goes to the ON state and the P-channel MOS transistor T125 goes to the OFF state. Also, the N-channel MOS transistor T113 goes to the OFF state and the N-channel MOS transistor T113 goes to the ON state. In this way, a difference of the potentials on the bit line Bj(7) is amplified.
In the sense amplifier section, a flip-flop of NAND gates N111 and N112 is provided and connected with the bit line Bj(7) of the pair via switches SW141 and SW142. The switches SW141 and SW142 are turned on in response to the read signal RD supplied from the memory control circuit 106. Thus, the potential difference is latched by the flip-flop. The output of the NAND gate N111 is connected with an inverter I114, and the output of the flip-flop is outputted to the latch section 108 via the inverter I114.
Next, the write operation of the first process in the conventional control driver when the size of image data is not larger than that of the screen of the display section 103 will be described with reference to FIGS. 4A to 4G. The image data is transferred from the image drawing unit 101 to the control driver 102 in synchronism with the timing signal, and latched by a latch section (not shown). The control driver 102 carries out the write operation of image data during the write period 0 to a4 in response to the display memory control signal from the memory control circuit 106. The display memory control signal contains a write signal WT, an X address, a Y address, a sense precharge control signal SPC, and a precharge signal PCB. The write period contains a precharge period, a data determination period and a data write period. The precharge period is a period 0 to a1, the data determination period is a period a1 to a2, and the data write period is a period a2 to a3.
Referring to FIGS. 4D and 4E, in the precharge period of the first process, the memory control circuit 106 sets the sense precharge control signal SPC to the high level and the precharge signal PCB to the low level in response to the memory control signal. As a result, the switches SW121 and SW122 are turned on to connect the bit lines Bj(7) and Bj′(7) of the memory cell section with the bit lines of the precharge section. Also, the P-channel MOS transistors T121, T122 and T123 are turned on so that the bit lines are precharged to a predetermined potential, and equalized.
Subsequently, in the data determination period, the signal SPC is set to the low level and the signal PCB is set to the high level. As a result, the switches SW121 and SW122 are turned off, and the P-channel MOS transistors T121, T122, and T123 are also turned off. Also, the image data latched by the latch section is supplied to the display memory section 107 in response to the timing signal. The bit line decoder 122 of the display memory section 107 decodes the X address of the display memory control signal and drives data bits based on the decode result, as shown in FIG. 4A.
Subsequently, in the data write period, as shown in FIGS. 4B and 4C, the switches SW111 and SW112 are turned on in response to the write signal WT so that the data bits are connected with the bit lines Bj and Bj′ of the pairs. As a result, the bit lines of the pair are set to different potentials based on the corresponding data bit. The word line decoder 121 of the display memory section 107 decodes the Y address to set one of the word lines to the high level to drive the word line WL1. As a result, for example, the N-channel MOS transistors T111 and T112 of the memory cell C11(7) are turned on. Thus, the data bit is latched or stored by the latch element.
Subsequently, at the time a3 of the data write period, the write signal WT is set to the low level so that the switches SW111 and SW112 are turned off. Also, the word line decoder 121 of the display memory section 107 sets the word line WL1 to the low level so that the N-channel MOS transistors T111 and T112 are turned off.
Subsequently, at the time a4, the sense precharge control signal SPC and the precharge signal PCB are set to the high level and the low level again, respectively. Thus, the write operation can be repeated.
Next, a read operation of the first process in the conventional control driver will be described. FIGS. 5A to 5G are timing charts showing the read operation in the conventional control driver. The memory control circuit 106 outputs the display memory control signal in response to the memory control signal. The display memory control signal contains a read signal RD, an X address, a Y address, the sense precharge control signal SPC, the precharge signal PCB, and a sense amplifier enable signal SE. A period 0 to b5 of the read operation contains a precharge period, a data read operation period, a sense operation period and a data output period. The precharge period is a period 0 to b1, the data read operation period is a period b1 to b2, the sense operation period is a period time b2 to b3, the data output period is period b3 to b4, and another period b4 to b5 is provided.
As shown in FIG. 5E, in the precharge period of the first process, the sense precharge control signal SPC is set to the high level so that the switches SW121 and SW122 are turned on to connect the bit lines Bj(7) and Bj′(7) of the memory cell section with the bit lines of the precharge section. Also, the precharge signal PCB is set to the low level. As a result, the P-channel MOS transistors T121, T122 and T123 are turned on so that the bit lines Bj(7) and Bj′(7) are precharged to predetermined potentials which are equalized.
Subsequently, in the data read operation period of the first process, the signal PCB is set to the high level. As a result, the P-channel MOS transistors T121, T122, and T123 are turned off, as shown in FIG. 5E, and the precharge operation is completed. The bit line decoder 122 selects all the bit line pairs based on the X address. Also, one of the word lines WLi is selected and driven to the high level by the word line decoder 121 based on the Y address, as shown in FIG. 5C. Thus, for example, the N-channel MOS transistors T111 and T112 connected with the word line WL1 are turned on. As a result, the data bit latched by the latch element of the memory cell C11(7) is outputted onto the bit lines Bj(7) and Bj′(7) of the pair.
Subsequently, in the sense operation period of the first process, as shown in FIG. 5D, the sense precharge control signal SPC is set to the low level so that the bit lines of the memory cell section is disconnected from the bit lines in the precharge circuit section and the sense amplifier section. At this time, the potentials of the bit lines in the precharge circuit section and the sense amplifier section are set sufficiently based on the data bit. As shown in FIG. 5E, the sense amplifier enable signal SE supplied from the memory control circuit 106 is set to the high level so that the switches SW131 and SW132 are turned on. Thus, the difference between the potentials on the bit lines is amplified.
Subsequently, in the data output period of the single transfer process, as shown in FIG. 5G, the read signal RD is set to the high level by the memory control circuit 106 so that the switches SW141 and 142 are turned on. As a result, the potential states on the bit lines are latched by the flip-flop. Then, the read out bit data is outputted from the inverter I114.
Then, during the data output period, the sense amplifier enable signal SE is set to the low level. Thereafter, at the time b4, the selected word line and the read signal are set to the low level. Thus, the bit data can be read out.
At the time b5, the precharge signal PCB is set to the low level again to repeat the read operation.
As described above, in the mobile terminal, when the size of the image data is larger than the size of the screen of the display section 103 and has the first image data and the second image data, the image drawing unit 101 transfers the first image data, the control driver 102 stores the first image data in the display memory section 107, and the first image data is displayed on the display section 103. When a scroll instruction is issued in response to an operation of the input unit by the user, the image drawing unit 101 transfers the second image data, the control driver 102 stores the second image data in the display memory section 107, and the second image data is displayed on the display section 103. In the mobile terminal, the first image data or the second image data is transferred every time the scroll instruction is issued, and stored in the display memory section 107. For this reason, the power consumption has become large.
For example, the image data is supposed to be an E-mail. In this case, when the mobile terminal receives the E-mail with a message longer than a usual message, there is a problem that the user (the user) can not understand the whole message once because the whole message can not be displayed on the display section 103.
In Japanese Laid Open Patent Application (JP-A-Heisei 9-281950), a method of storing message data in a display memory section as a bit map is disclosed. The content of the display memory is shifted in accordance with a scroll operation. In this case, in order to prevent increase of the consumption power when the image data is stored in the display memory every time a screen is scrolled, only the pixels of the changed image data are transferred from the image drawing unit, resulting in reduction of the consumption power. However, in this conventional example, even if the consumption power per the transfer reduces, the consumption power has become large every time the scroll instruction is carried out. The increase of the consumption power is a large problem for the mobile terminal. In order to maintain the available time during which the scroll instruction can be used, the power supply must have a large size. It damages the characteristic of the mobile terminal, i.e., the smallness and light weight.
Also, a method of increasing the memory capacity of a display memory is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 7-295937). In this conventional example, an image memory is provided to have a larger capacity than the capacity of the display memory. A mouse ball is provided to detect a quantity of movement and a direction of the movement in a scroll operation. A calculation process section improves the scroll operability by reading the movement data. In this conventional example, the image data which has an area wider than the display area of a display section is stored in the image memory and a display position on the image memory is changed when the scroll is carried out. Therefore, in this conventional example, it is sufficient that the image data transfer is carried out once. However, because the chip area increases by increasing the memory capacity of the display memory, resulting in increase of the cost of the chip.
Also, an image data processing apparatus is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 7-152905). In this conventional example, a memory section is provided to store image data. An address generating section generates an address to specify a storage position of the image data stored in the memory section. An address control section is provided to control the address generating section such that a specification order of the addresses generated by the address generating section is controlled to control an output order of the image data from the memory section.
Also, a method of a display apparatus is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 9-81084). In this conventional example, a part of display data is given in a scroll display, and a control unit controls for it to be displayed on a predetermined partial region of an image display apparatus. Thus, a time for updating a display screen is made short in the scroll display. Also, during the scroll display, a quantity of data to be transferred is reduced.
Also, a matrix display unit is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 10-74064). The matrix-type display unit of this conventional example aims at reduction of consumption power. A plurality of display pixels are arranged in a matrix in 2-dimensional directions of display screen. A plurality of wiring lines are arranged in horizontal and vertical directions. A plurality of first storage elements stores first display data in response to a first screen display timing. A motion detection section compares the first display data and second display data to detect existence or non-existence of a motion of an image, when the second display data is supplied to a second screen display timing subsequent to the first screen display timing. A calculation section determines a motion quantity of the image in a pixel unit when the motion of the image is detected. A display control section controls such that a part of the second display data is displayed on a position corresponding to the detected motion quantity when the motion of the image is detected, and a part of the first display data is displayed on the original position.
Also, a display unit is disclosed in Japanese Laid Open Patent Application (JP-P2001-222276A). In this conventional example, the display unit contains a RAM built-in driver. First and second bus lines transfer a still picture data and a video picture. A RAM stores the still picture data and the video picture data. A first control circuit carries out a write control and a read control to the RAM. A second control circuit operates independently from the first control circuit and carries out a read control of the still picture data and the video picture data as display data, and drives a display section.